My research is building a heterogeneity of solutions co-optimized across the algorithm, memory subsystem, hardware architecture, and silicon stack to generate breakthrough advances in arithmetic performance, compute density and flexibility, and energy efficiency for on-chip machine learning, and emerging compute-intensive applications. I also bear a keen interest in agile chip design methodologies.
My work received Best Paper Award at DAC (2020), ACM SIGDA Research Highlights (2021), IEEE MICRO Top Picks Honorable Mention (2022) accolades, and has been recognized with a NVIDIA Graduate Fellowship (2021), and an IEEE SSCS Predoctoral Achievement Award (2021).
I received my Ph.D. in Electrical Engineering from Harvard University. Prior to debuting my doctoral studies, I was a senior engineer at Intel, where I designed mixed-signal transceiver and peripheral circuits for EMIB-based chips.
- VLSI systems (i.e., number systems, schedulers, architectures, circuits, devices, and chips) for emerging AI and compute-intensive applications
- AI for VLSI (e.g., AI-aided hardware and compiler design, AI-based smart power management ICs)
- Heterogenous system integration (2D, 2.5D, 3D chiplets and systems-in-package)
- Agile chip development
|Oct, 2023||Our paper on eDRAM-based on-device ML training will appear at HPCA’24!|
|Aug, 2023||Beginning a post-doc at NVIDIA Research.|
|May, 2023||Our paper on model-architecture co-design for efficient on-device ML training using on-chip embedded DRAMs is released on Arxiv.|
|May, 2023||Accepted offer to join Stanford University as an Assistant Professor starting Sept. 2024.|
|Apr, 2023||Successfully defended my PhD thesis.|
Selected Papers [full list]
- ISSCCA 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power ManagementIn 2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023
- JSSCA 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNsIEEE Journal of Solid-State Circuits, 2023
- ArXivCAMEL: Co-Designing AI Models and Embedded DRAMs for Efficient On-Device Learning2023
- MICROEdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP InferenceIn MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Best Paper AwardAlgorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning InferenceIn 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020